1. Technical Field of the Invention
The present invention relates to static frequency divider circuits.
2. Description of Related Art
A static frequency divider usually refers to a frequency divider consisting of two latches connected in series with a feedback path connected between. A commonly used static frequency divider 10 circuit structure is illustrated in FIG. 1. Its configuration and operation are readily understood by those skilled in the art. The divider 10 includes a first (or master) latch 12 and a second (or slave) latch 14 that are interconnected by both a series path and a feedback path. The first and second latches 12 and 14 are implemented as current mode logic (CML) D-type latches. CML is preferred because it offers fully differential routing of signal paths.
The first latch 12 includes a reading (or track) branch 16 and a latching (or latch) branch 18 as well as a double emitter-follower circuit 30(1). Similarly, the second latch 14 includes a reading (track) branch 20 and a latching (latch) branch 22 and double emitter-follower circuit 30(2). The reading and latching branches are each formed from a pair of transistors (for example, M3/M4 and M5/M6) with common collector connected load resistors (for example, R1 and R2) and positive parallel feedback from the emitter followed circuits 30. Each of the first and second latches 12 and 14 further include a steering branch 21 coupled to both the reading and latching branches and operable responsive to clock signals to steer current through either of the reading or latching branches. The steering branch is also formed from a pair of transistors (for example, M1/M2) whose collectors are connected to the coupled emitters of the paired transistors for the reading and latching branches.
For each latch, the differential circuit inputs are provided at the base terminals of the pair of transistors for the reading branch and the differential circuit outputs are provided at the emitter terminals of a pair of transistors in each of the double emitter-follower circuits 30 connected to the latching branch. The differential clock input to each latch is provided at the base terminals of the pair of transistors for the steering branch.
The connection of the two CML D-type latches in series (differential output to input) with inverted clock signals applied to the differential clock inputs (in the steering branches 21) forms a master-slave D-type flip-flop circuit of known configuration. A ½ frequency divider is then formed from this master-slave flip-flop configuration by connecting the differential outputs of the slave flip-flop to the differential inputs of the master flip-flop.
The double emitter-follower circuits 30(1) and 30(2), each composed of transistors A, B, C and D, are provided within each latch 12 and 14 to improve the operating speed of the divider 10. More specifically, transistors A and C are connected in a cascade emitter-follower fashion as a first emitter-follower and transistors B and D are connected in a cascade emitter-follower fashion as a second emitter-follower. With respect to the differential series path, the first emitter follower circuit using transistors A and C interconnects the first and second BALLSACK latches such that the output(bar) of the first latch 12 (at the emitter of transistor C) is connected to the input of the second latch 14 while the second emitter follower circuit using transistors B and D interconnects the first and second latches such that the output of the first latch (at the emitter of transistor D) is connected to the input(bar) of the second latch. With this first and second latch 12 and 14 negative differential series path interconnection implementation, the differential feedback path must be positive. So, in the differential feedback path, the first emitter follower circuit using transistors A and C interconnects the second and first latches 14 and 12 such that the output(bar) of the second latch (at the emitter of transistor C) is connected to the input(bar) of the first latch while the second emitter follower circuit using transistors B and D interconnects the second and first latches such that the output of the second latch (at the emitter of transistor D) is connected to the input of the first latch.
While the included double emitter-follower circuits 30 assist with enhancing the operating speed of the divider 10, it is still not fast enough and stable enough to operate at some microwave speeds. As the operating frequency of the divider 10 increases, difficulties arise with respect to the operation of transistors C and D. More specifically, the issue of transistor breakdown voltage is an important concern in high speed circuits that are designed with advanced process technologies such as SiGe. With a transition frequency approaching or above 100 GHz, the base-emitter voltages for the transistors will not scale down with the desired shrinking size of those transistors. Take, for example, the transistors C and D in FIG. 1 which will see, at least, 2*Vbe across their collectors and emitters. Suppose the BVceo (breakdown voltage) is 1.7V for these transistors and that Vbe for these transistors is 0.85V. In this case, then 2*Vbe is 1.7V. Operating these transistors at or a little bit above BVceo is possible in some cases, but is not preferred for ensuring proper transistor operation over an extended period of time. Still further, in the double emitter-follower circuits used in FIG. 1, it is very difficult in that operating environment to optimize the sizes of transistors A, B, C and D to get the highest possible operation.
Accordingly, a need exists for a static frequency divider that addresses the foregoing problems, and other problems, and further which can provide for improved operation at microwave frequencies.